Synopsys announced the expansion of its memory Verification IP (VIP) portfolio to include key titles for the mobile industry. Synopsys memory VIP is based on a native SystemVerilog architecture to enable enhanced ease of use, integration and configurability. With these advanced features, project teams using the JEDEC UFS, MIPI UniPro and JEDEC eMMC protocols can further accelerate verification closure of mobile block, subsystem and system-on-chip (SoC) designs.
"The adoption of M-PHY and UniPro into JEDEC's UFS memory interface provides lower power and higher performance and enables the industry to stay on the leading edge of the performance curve," said Joel Huloux, chairman of MIPI Alliance.
"Synopsys' feature-rich VIP and test suites with built-in coverage for the UFS, UniPro and M-PHY specifications strengthen the ecosystem required to enable fast development of mobile and mobile-related products, and it enables higher-confidence compliance verification."
VIP for the emerging UFS and UniPro protocols also includes self-contained compliance test suites to accelerate verification closure and eliminate the tasks of developing a verification environment and tests. The test suites are delivered as native SystemVerilog source code for improved reuse, extensibility and debug. The JEDEC eMMC VIP includes support for eMMC Card and Host. All verification IP and test suites are based on a consistent SystemVerilog UVM architecture to enable easy adoption.
Synopsys' broad portfolio of bus, interface and memory VIP includes built-in coverage and verification plans to enable coverage closure. It also includes support for Verdi Protocol Analyzer to provide protocol-aware debug. Synopsys VIP for the JEDEC UFS, MIPI UniPro and JEDEC eMMC memory protocol specifications provides a comprehensive set of protocol, methodology, verification and productivity features, enabling users to achieve rapid verification convergence.
"We have worked closely with our customers and the standards boards to provide verification IP for the latest protocols, including technology to enable fast deployment of VIP into verification environments and to rapidly achieve verification closure," said Debashis Chowdhury, vice president of R&D for the Synopsys Verification Group.
"The mobile market segment is extremely competitive, with designers at all levels of the product hierarchy continually striving to achieve more performance with increased functionality at the lowest levels of power consumption and cost. On-time availability of emerging protocols and the latest versions of current protocols enable designers to achieve their verification goals and hit project schedules."
