Texas Instruments (TI) introduced the AFE5818 and AFE5816 families, the industry's first 16-channel ultrasound analog front ends (AFEs). The new AFEs integrate a range of features to maximize image quality and performance while minimizing power consumption and system cost.
To optimize system efficiency, these families offer multiple versions with and without a demodulation block and JESD204B interface option, which further simplifies board layout and provides cost savings. The new families also offer low power consumption for the noise performance achieved, enabling portable solutions that offer better imaging performance without negatively impacting the power budget.
Features:
‧ Highest integration: The AFE5818 and AFE5816 families are the industry's first 16-channel simultaneously sampling AFEs, enabling system-level optimization.
‧ Minimal power consumption: The AFE5818 and AFE5816 offer power consumption as low as 94 mW and 52 mW per channel, respectively — 33 percent better per channel than the competition.
‧ JESD204B interface: The AFE58JD18 and AFE58JD16 include a 5-Gbps JESD204B serial interface, reducing ultrasound system data I/O routing by as much as 80 percent compared to other data interface standards and enabling a data rate of up to 6.4 Gbps. This standard interface creates a seamless connection to high-performance processors such as TI's 66AK2L06 multicore processor.
‧ Digital time gain compensation (DTGC): The AFE58JD16 and AFE5816 include a DTGC engine with 0.125-dB resolution, which reduces noise and power consumption. DTGC also reduces the need for external components, compared to traditional analog time gain compensation.
‧ Digital demodulator: The AFE58JD18 and AFE58JD16 also feature an on-chip digital demodulator, which conditions 16 channels of data from RF to a baseband frequency. This reduces the load on the system processing engine to enable lower latency and higher image quality.
Complementing the AFE5818 and AFE5816 families is TI's ADS52J90, a new 16-channel high-speed analog-to-digital converter (ADC) that can be configured for up to 32 inputs, for ultrasound receiver designs that require greater front end design flexibility. The ADC also offers the on-chip digital demodulator for reducing processor or FPGA costs, as well as a low-voltage differential signaling (LVDS) or JESD204B serial interface for faster data rates.
