Synopsys, Inc. today announced new extensions to its open-source Interconnect Technology Format (ITF) which enable modeling of complex device and interconnect parasitic effects at the advanced 10-nanometer (nm) process node.
The new extensions include modeling of variation effects due to multi-patterning technology (MPT). Synopsys collaborated with the members of the Interconnect Modeling Technical Advisory Board (IMTAB), an IEEE-ISTO Federation Member Program, to define and ratify these new extensions. They will be available in the upcoming open-source ITF version 2015.06.
"Enabling productive design and analysis for a colored layout flow, while also providing a solution to model increased parasitic variation due to MPT approaches, is critical at 10 nm," said Bari Biswas, vice president of engineering for extraction solutions at Synopsys and chair of IMTAB.
"Through our collaboration with IMTAB members and leading foundries, Synopsys developed an innovative solution that extended the existing variation models in ITF to become intrinsically color-aware to more accurately model mask dependency while fitting seamlessly into a designer's existing flow."
"ITF continues to be the cornerstone of parasitic modeling in the semiconductor industry," said Marco Migliaro, President, IEEE-ISTO.
"The new 10-nm models represent the fourth successive generation of model extensions fostered by the IMTAB consortium. IEEE-ISTO looks forward to continuing our support of the IMTAB mission to drive increased tool interoperability through the ITF common open-source modeling format."
MPT is an evolution of the double patterning technology (DPT) first introduced by foundries at the 20-nm process node, and it further extends the use of immersion lithography to 10 nm and below. However, MPT imposes tighter requirements on design implementation and analysis to support layout decomposition into different masks (coloring) and manage increased variation due to misalignment of the multiple masks.
Synopsys' advanced MPT solution ratified by IMTAB for 10 nm includes color-aware models that cover all leading foundry manufacturing techniques including sequential litho-etch patterning, for example, triple patterning (LELELE) and quadruple patterning (LELELELE), as well as spacer-assisted/self-aligned patterning, for example, self-aligned double patterning (SADP) and self-aligned quadruple patterning (SAQP).
In addition to MPT modeling, Synopsys has introduced other ITF extensions approved by IMTAB for more accurate via resistance and device capacitance extraction at advanced FinFET process nodes. At 10nm, via resistivity has increased significantly with growing conductor environment context, so the existing self-aligned via resistance variation model has been extended to include coverage from top and bottom conductors.
In addition, new ITF models have been added to accurately extract the floating gate to diffusion contact capacitance for polycide on diffusion edge (PODE) devices and spacer dielectric between gate polycide and contact, both of which are critical to regulating device performance.
