Synopsys introduced the industry's first complete LPDDR4 IP solution, which includes Synopsys' DesignWare LPDDR4 multiPHY, Enhanced Universal DDR Memory Controller (uMCTL2) and verification IP (VIP), as well as hardening and signal integrity services. Synopsys' DesignWare LPDDR4 IP solution supports all key LPDDR4 features, including up to 3200 Mbps performance and features to reduce power consumption, delivering a low-power memory solution for mobile and graphics-intensive system-on-chips (SoCs).
"LPDDR4 technology enables new, lower power mobile devices with higher graphics capabilities that deliver an immersive and exhilarating user experience," said Dan Skinner, director of DRAM architecture at Micron Technology.
"Micron is leading the way on this new mobile memory technology and our customers will be first to market with the help of Synopsys, which is providing early availability of a complete LPDDR4 IP solution before the standard is finalized. Together we're building a LPDDR4 ecosystem to jump-start these innovative, mobile designs."
The DesignWare LPDDR4 IP solution supports data rates up to 3200 Mbps to meet the demands of faster processors, high-resolution displays, HD video and graphics-intensive games in mobile SoC applications. Fast frequency switching matches memory bandwidth to the device workload to optimize performance and power consumption.
The DesignWare LPDDR4 IP solution can reduce power consumption per bit transferred by incorporating multiple power-saving features such as low-power modes (including power-down, self-refresh, and deep power-down), clock gating and power down of sections of the PHY that are not in use at a given moment. These features can extend the battery life of mobile devices and support consumers' increasing requirements for thin and light devices.
To minimize design risk, the DesignWare LPDDR4 IP solution includes backward compatibility with LPDDR3 and DDR3/4 SDRAMs to simplify the design transition from one SDRAM standard to the next.
In addition, the LPDDR4 IP supports a split PHY implementation to permit designers to distribute the IP around the SoC, optimizing the interface for area-efficient PoP assembly and offering a low-risk evolutionary path from previous-generation mobile memories.
Designers can take advantage of Synopsys' DDR hardening and signal integrity services to harden the LPDDR4 multiPHY and to analyze the signal integrity of the entire system (silicon, package and PCB), easing IP integration and reducing potential risks in the use of advanced manufacturing technologies.
"Synopsys is focused on providing IP on the leading edge of both functionality and process," said John Koeter, vice president of marketing for IP and prototyping at Synopsys.
"The LPDDR4 solution announced today builds upon our 15 years of experience in the DDR IP space as well as our experience with customers successfully implementing DesignWare DDR IP in their SoCs and electronic systems."
